The present disclosure relates to a pulsed flip-flop and, more particularly to a pulsed flip-flop adjusting a pulse width.
A flip-flop includes a master-slave flip-flop and a pulsed flip-flop. The master-slave flip-flop connects two flip-flops in series. The master flip-flop receives data synchronized with a rising edge of a clock, and a slave flip-flop outputs data synchronized with a falling edge of a clock. When an input data value changes after a clock is shifted from low to high, the master flip-flop cannot store the input data value. Thus, it takes more time for setup of the input data.
On the other hand, a pulsed flip-flop receives a clock, generates an internal clock, and then outputs an inputted data during an interval corresponding to an internal pulse width. Accordingly, when data is inputted after a clock is shifted from low to high, the pulsed flip-flop can store and output the data. That is, since the pulse flip-flop has a short setup time for a clock of the input data, it is appropriate for use in a semiconductor device that requires high-speed operations. The pulsed flip-flop has disadvantages, however, related to a hold time. For example, the input data change during a interval corresponding to a pulse width of an internal pulse. That is, when an input data value changes during an interval corresponding to a pulse width of an internal pulse, an output value changes because the data value that is inputted later is stored and outputted.
Additionally, in the pulsed flip-flop, hold time characteristics deteriorate in a low-voltage operation. As described above, the pulse flip-flop needs to maintain data longer than a pulse width of an internal pulse, and delay rates of an internal pulse and an input data are different in a low-voltage operation. Therefore, hold time characteristics deteriorate. That is, since the pulse width of an internal pulse becomes longer than the input data delay, hold time error can occur.